Electronic Design

ATE – Design for Test – Putting Memory to the Test in Nanometer Designs

Memory test at-speed isn't easy but can be achieved by balancing test selection, area overhead, and test-time constraints. The semiconductor industry has intensified its focus on yield issues to meet ...
Business Wire

Keithley Adds Support for Non-Volatile Memory, Very Low Frequency C-V, and Increased Parallel Testing to Semiconductor Parameter Analyzer

CLEVELAND--(BUSINESS WIRE)--Keithley Instruments, Inc., a world leader in advanced electrical test instruments and systems, has introduced a variety of enhancements for its award-winning Model ...
Electronic Design

The Challenges of Memory Mix Test

The variety of different test methodologies combined with today�s mixture of memory devices creates a complex test profile. The manufacturing test floor hums with activity; a range of memory devices ...

New KV cache compaction technique cuts LLM memory 50x without accuracy loss

MIT researchers developed Attention Matching, a KV cache compaction technique that compresses LLM memory by 50x in seconds — ...
Nature

Magnetic Memory Techniques for Stress and Damage Assessment in Ferromagnetic Materials

Magnetic memory techniques have emerged as a promising non‐destructive evaluation (NDE) approach to assess the stress state and detect early damage in ferromagnetic materials. By utilising the ...
EDN

Alternative techniques accelerate flash-memory-programming speeds

No matter which flash-memory-programming method you use, optimization of the programming algorithm is a key consideration. It has the potential to reduce flash-programming time and, therefore, ...